SPI2 test based on DMA transfers/interrupts Connect MOSI to MISO pin.
Toolkit:STM Development System
Location:/bipom/devtools/STM32/examples/spi2dma
SPI_InitTypeDef SPI_InitStructure; DMA_InitTypeDef DMARX_InitStructure; DMA_InitTypeDef DMATX_InitStructure; GPIO_InitTypeDef GPIO_InitStructure; UBYTE SPI2_MASTER_Buffer_Tx[BufferSize] = {0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, 0x08, 0x09, 0x0A, 0x0B, 0x0C, 0x0D, 0x0E, 0x0F, 0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x16, 0x17, 0x18, 0x19, 0x1A, 0x1B, 0x1C, 0x1D, 0x1E, 0x1F, 0x20}; UBYTE SPI2_MASTER_Buffer_Rx[BufferSize]={0}; volatile TestStatus TransferStatus = FAILED; volatile int CurrDataCounterEnd = 1; //******************************************************************************** int main (void) { delayMs(250); UINT testNum =1; ERRCODE ec=SUCCESS; tprintf("\n\rMini-Max/STM32F1"); tprintf("\n\rSPI2/DMA TEST REV 1.01"); // ec = Spi2Dma_Test(); tprintf("\r\nTEST 0 "); if(SUCCESS == ec) tprintf("PASSED"); else tprintf("FAILED"); for(;;) { delayMs(500); ec = Spi2Dma_NextTest(); tprintf("\r\nTEST %u ",testNum++); if(SUCCESS == ec) tprintf("PASSED"); else tprintf("FAILED"); } return 0; } //******************************************************************************** ERRCODE Spi2Dma_Test(void) { ERRCODE ec = SUCCESS; /* Configure DMA interrupts */ NVIC_Configuration(); /* Configure clocks */ RCC_AHBPeriphClockCmd(SPI2_MASTER_DMA_CLK, ENABLE); RCC_APB2PeriphClockCmd(SPI2_MASTER_GPIO_CLK, ENABLE); RCC_APB1PeriphClockCmd(SPI2_MASTER_CLK, ENABLE); /* Configure SPI_MASTER pins: MISO, SCK and MOSI */ GPIO_InitStructure.GPIO_Pin = SPI2_MASTER_PIN_MISO | SPI2_MASTER_PIN_SCK | SPI2_MASTER_PIN_MOSI; GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz; GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP; GPIO_Init(SPI2_MASTER_GPIO, &GPIO_InitStructure); /* Configure RX DMA */ DMA_DeInit(SPI2_MASTER_Rx_DMA_Channel); DMARX_InitStructure.DMA_PeripheralBaseAddr = (uint32_t)SPI2_MASTER_DR_Base; DMARX_InitStructure.DMA_MemoryBaseAddr = (uint32_t)SPI2_MASTER_Buffer_Rx; DMARX_InitStructure.DMA_DIR = DMA_DIR_PeripheralSRC; DMARX_InitStructure.DMA_BufferSize = BufferSize; DMARX_InitStructure.DMA_PeripheralInc = DMA_PeripheralInc_Disable; DMARX_InitStructure.DMA_MemoryInc = DMA_MemoryInc_Enable; DMARX_InitStructure.DMA_PeripheralDataSize = DMA_PeripheralDataSize_Byte; DMARX_InitStructure.DMA_MemoryDataSize = DMA_MemoryDataSize_Byte; DMARX_InitStructure.DMA_Mode = DMA_Mode_Normal; DMARX_InitStructure.DMA_Priority = DMA_Priority_VeryHigh; DMARX_InitStructure.DMA_M2M = DMA_M2M_Disable; DMA_Init(SPI2_MASTER_Rx_DMA_Channel, &DMARX_InitStructure); /* Configure TX DMA */ DMA_DeInit(SPI2_MASTER_Tx_DMA_Channel); DMATX_InitStructure.DMA_PeripheralBaseAddr = (uint32_t)SPI2_MASTER_DR_Base; DMATX_InitStructure.DMA_MemoryBaseAddr = (uint32_t)SPI2_MASTER_Buffer_Tx; DMATX_InitStructure.DMA_DIR = DMA_DIR_PeripheralDST; DMATX_InitStructure.DMA_BufferSize = BufferSize; DMATX_InitStructure.DMA_PeripheralInc = DMA_PeripheralInc_Disable; DMATX_InitStructure.DMA_MemoryInc = DMA_MemoryInc_Enable; DMATX_InitStructure.DMA_PeripheralDataSize = DMA_PeripheralDataSize_Byte; DMATX_InitStructure.DMA_MemoryDataSize = DMA_MemoryDataSize_Byte; DMATX_InitStructure.DMA_Mode = DMA_Mode_Normal; DMATX_InitStructure.DMA_Priority = DMA_Priority_VeryHigh; DMATX_InitStructure.DMA_M2M = DMA_M2M_Disable; DMA_Init(SPI2_MASTER_Tx_DMA_Channel, &DMATX_InitStructure); /* Configure SPI MASTER */ SPI_InitStructure.SPI_Direction = SPI_Direction_2Lines_FullDuplex; SPI_InitStructure.SPI_Mode = SPI_Mode_Master; SPI_InitStructure.SPI_DataSize = SPI_DataSize_8b; SPI_InitStructure.SPI_CPOL = SPI_CPOL_High; SPI_InitStructure.SPI_CPHA = SPI_CPHA_1Edge; SPI_InitStructure.SPI_NSS = SPI_NSS_Hard; SPI_InitStructure.SPI_BaudRatePrescaler = SPI_BaudRatePrescaler_32; SPI_InitStructure.SPI_FirstBit = SPI_FirstBit_MSB; SPI_InitStructure.SPI_CRCPolynomial = 7; SPI_Init(SPI2_MASTER, &SPI_InitStructure); /* Enable SPI2_MASTER Rx request */ SPI_I2S_DMACmd(SPI2_MASTER, SPI_I2S_DMAReq_Rx, ENABLE); /* Enable SPI2_MASTER Tx request */ SPI_I2S_DMACmd(SPI2_MASTER, SPI_I2S_DMAReq_Tx, ENABLE); /* Enable DMA1 Channel4 Transfer Complete interrupt */ DMA_ITConfig(DMA1_Channel4, DMA_IT_TC, ENABLE); /* Enable SPI_MASTER */ SPI_Cmd(SPI2_MASTER, ENABLE); /* Enable DMA1 Channel4 */ DMA_Cmd(SPI2_MASTER_Rx_DMA_Channel, ENABLE); /* Enable DMA1 Channel5 */ DMA_Cmd(SPI2_MASTER_Tx_DMA_Channel, ENABLE); /* Wait the end of transmission */ while (CurrDataCounterEnd != 0){} /* Check the correctness of written data */ TransferStatus = Buffercmp(SPI2_MASTER_Buffer_Rx, SPI2_MASTER_Buffer_Tx, BufferSize); /* TransferStatus = PASSED, if the transmitted and received data are equal */ /* TransferStatus = FAILED, if the transmitted and received data are different */ // if (PASSED==TransferStatus) ec = SUCCESS; else ec = ERROR; return ec; } //******************************************************************************** TestStatus Buffercmp(UBYTE* pBuffer1, UBYTE* pBuffer2, uint16_t BufferLength) { while (BufferLength--) { if (*pBuffer1 != *pBuffer2) { return FAILED; } pBuffer1++; pBuffer2++; } return PASSED; } //******************************************************************************** void NVIC_Configuration(void) { NVIC_InitTypeDef NVIC_InitStructure; /* Enable DMA1 channel4 IRQ Channel */ NVIC_InitStructure.NVIC_IRQChannel = DMA1_Channel4_IRQn; NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = 0; NVIC_InitStructure.NVIC_IRQChannelSubPriority = 0; NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE; NVIC_Init(&NVIC_InitStructure); } //******************************************************************************** void DMA1_Channel4_IRQHandler(void) { /* Test on DMA1 Channel4 Transfer Complete interrupt */ if(DMA_GetITStatus(DMA1_IT_TC4)) { /* Get Current Data Counter value after complete transfer */ CurrDataCounterEnd = DMA_GetCurrDataCounter(DMA1_Channel4); /* Clear DMA1 Channel4 Half Transfer, Transfer Complete and Global interrupt pending bits */ DMA_ClearITPendingBit(DMA1_IT_GL4); } } //******************************************************************************** ERRCODE Spi2Dma_NextTest(void) { ERRCODE ec = SUCCESS; int i; // Clear Rx buffer for(i=0; i<BufferSize; i++) SPI2_MASTER_Buffer_Rx[i]=0; /* */ CurrDataCounterEnd = 1; /* Configure RX DMA */ DMA_DeInit(SPI2_MASTER_Rx_DMA_Channel); DMA_Init(SPI2_MASTER_Rx_DMA_Channel, &DMARX_InitStructure); /* Configure TX DMA */ DMA_DeInit(SPI2_MASTER_Tx_DMA_Channel); DMA_Init(SPI2_MASTER_Tx_DMA_Channel, &DMATX_InitStructure); // /* Enable SPI2_MASTER Rx request */ SPI_I2S_DMACmd(SPI2_MASTER, SPI_I2S_DMAReq_Rx, ENABLE); /* Enable SPI2_MASTER Tx request */ SPI_I2S_DMACmd(SPI2_MASTER, SPI_I2S_DMAReq_Tx, ENABLE); /* Enable DMA1 Channel4 Transfer Complete interrupt */ DMA_ITConfig(DMA1_Channel4, DMA_IT_TC, ENABLE); // /* Enable DMA1 Channel4 */ DMA_Cmd(SPI2_MASTER_Rx_DMA_Channel, ENABLE); /* Enable DMA1 Channel5 */ DMA_Cmd(SPI2_MASTER_Tx_DMA_Channel, ENABLE); /* Wait the end of transmission */ while (CurrDataCounterEnd != 0){} /* Check the correctness of written data */ TransferStatus = Buffercmp(SPI2_MASTER_Buffer_Rx, SPI2_MASTER_Buffer_Tx, BufferSize); /* TransferStatus = PASSED, if the transmitted and received data are equal */ /* TransferStatus = FAILED, if the transmitted and received data are different */ // if (PASSED==TransferStatus) ec = SUCCESS; else ec = ERROR; return ec; }